(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the salicide formation process in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of embedded dynamic random ad access memory (EDRAM) integrated circuit devices, logic and memory devices are fabricated on the same chip. Logic devices are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance. In memory devices, silicide is used only on the gate regions, not on the source and drain regions because of junction leakage problems.
In preparing for silicidation, the areas not to be silicided, such as the source/drain regions in the memory areas, must be protected while the areas to be silicided are exposed. In the conventional process, silicon nitride spacers are formed on the sidewalls of the gate electrodes in order to prevent source/drain to gate bridging after silicidation. A barrier and anti-reflective coating (BARC) layer is deposited over the gate electrodes followed by a layer of photoresist. The photoresist is patterned and then etched back using a dry etching process to expose the areas to be silicided. However, because of poor etching selectivity, the silicon nitride spacers are damaged by the etch back process. This leads to source/drain to gate bridging of the salicide. It is desired to prevent damage to the silicon nitride spacers during patterning for silicidation.
U.S. Pat. No. 5,486,424 to Nakato et al teaches a method of forming a silylated photoresist layer and etching it back. U.S. Pat. No. 4,702,993 to White et al shows treatment of a polyimide planarizing layer underlying an electron beam resist. U.S. Pat. No. 5,547,812 to Collins et al discusses the use of the resist developer trimethylammonium hydroxide (TMAH) as the industry standard. U.S. Pat. No. 5,597,983 to Nguyen et al teaches the use of TMAH in removing polymer buildup within a via.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of silicidation in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for resist planarization in the formation of a silicidated gate in the fabrication of integrated circuits.
Yet another object is to use resist planarization to prepare to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device.
Yet another object is to use resist planarization to prepare to form salicided gate and source/drain regions in the logic circuits of an embedded memory integrated circuit device while protecting areas within the memory circuits that are not to be silicided.
A still further object of the invention is to use resist planarization to prepare to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device wherein silicon nitride spacers are not damaged.
In accordance with the objects of the invention, a method of using resist planarization to prepare for silicidation while protecting silicon nitride spacers in the fabrication of integrated circuits is achieved. Field oxide areas are formed on a semiconductor substrate surrounding and electrically isolating a logic device area and a memory device area. Polysilicon gate electrodes and associated source/drain regions are formed in the device areas. Silicon nitride spacers are formed on the sidewalls of the polysilicon gate electrodes. A silicon oxide layer is deposited overlying the polysilicon gate electrodes and source/drain regions. The silicon oxide layer is covered with a photoresist layer. The photoresist layer is developed until the silicon oxide layer overlying the polysilicon gate electrodes is exposed and the photoresist layer is below the tops of the polysilicon gate electrodes. The exposed silicon oxide layer is etched away whereby the tops of the polysilicon gate electrodes are exposed and wherein the silicon nitride spacers are undamaged by the etching. The photoresist layer is removed. A photoresist mask is formed covering the memory device area. All of the silicon oxide layer not covered by the photoresist mask in the logic device area is etched away and the photoresist mask is removed. Thereafter, a layer of titanium is deposited over the semiconductor substrate. The semiconductor substrate is annealed whereby the titanium layer is transformed into a titanium silicide layer over the gate electrodes and over the source/drain regions in the logic area not covered by the silicon oxide layer. The unreacted titanium layer overlying the spacers, field oxide regions, and silicon oxide layer is removed to leave the titanium silicide layer only on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source/drain regions associated with the gate electrodes in the logic device area to complete fabrication of the integrated circuit device.